Survey on Timing Error Detection and Correction Methods for Fir Filter Applications

This paper presents the literature review on the various timing error analysis techniques involved in attaining power reduction in several computing applications, specifically for digital signal processing. FIR filters are widely used because they have linear phase characteristics, guarantee stability and are easy to implement with multipliers, adders and delay elements. The development of a high-performance FIR filter is crucial in order to satisfy the demands of various applications, including real-time, low power, low cost, and compact space. Using a razor flip-flop to scale voltage is a clever way to get rid of the supply voltage margin. The technique of Dynamic Voltage Scaling (DVS) in conjunction with Razor is employed to identify timing issues on the Critical Path. In DSP based applications, image compression and video compression are based on error tolerant; if there are errors in the intermediate outputs it will not form substantial reduction in final output quality. In this paper various Razor approach to Dynamic voltage scaling and Razor Flip-flops in filtering applications are discussed and extensive survey on features of FIR Filter design was reported. In this paper, various types of timing error detection and correction method is discussed to achieve low power consumption, less area, high speed and reduced computation time. Razor based voltage scaling can be implemented for filter application.